Packaged semiconductor dies, including memory chips, microprocessor chips, and imager chips, typically include a semiconductor die mounted on a substrate and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and imager devices, as well as bond pads electrically connected to the functional features. The bond pads can be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry. Within some packages, semiconductor dies can be stacked upon and electrically connected to one another by individual interconnects placed between adjacent dies. In such packages, each interconnect can include a conductive material (e.g., solder) and a pair of contacts on opposing surfaces of adjacent dies. For example, a metal solder can be placed between the contacts and then reflowed so that it reacts with the metal at each of the contacts to form a conductive joint.
One challenge with traditional solder joints is that solder can migrate or spread during reflow. For example, the solder can be displaced when it is squeezed between the metal contacts. Also, certain forces, such as surface tension, can cause the solder to wick away from a conductive surface and onto other surfaces. One specific challenge occurs when the solder wicks onto and forms an intermetallic material on the sidewalls of a metal contact. Such intermetallic materials on the sidewalls can ultimately degrade the overall electrical and/or thermal conductively of the contact. For example, conventional tin/copper intermetallic materials can reduce the overall thermal conductivity of a copper-based contact. Further, in vertical interconnects (e.g., copper posts), the solder can consume a substantial amount of metal, which can cause the interconnect to slump and/or form voids in the sidewalls (e.g., due to Kirkendall voiding).